1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor and, more particularly, to a semiconductor device with a reduced size and to a fabrication process therefor.
2. Description of Related Arts
To meet requirements for high density integration of semiconductor devices on a printed circuit board, the size of the semiconductor devices has been reduced.
FIG. 21 is a schematic diagram illustrating a conventional semiconductor device of the most common construction (hereinafter referred to as "common semiconductor device"). FIG. 22 is a plan view of the common semiconductor device of FIG. 21. As shown, the semiconductor device has a semiconductor chip 32 having electrodes 31, leads 33 serving as external connection terminals, wires 34 respectively connecting the electrodes 31 of the semiconductor chip 32 to the leads 33, and a resin sealer 35.
The electrodes 31 are disposed on a surface of the semiconductor chip 32 formed with circuits (not shown). The resin sealer 35 serves to protect from an exterior environment the semiconductor chip 32, the wires 34 and the circuits formed around regions where the wires 34 are connected to the leads 33. A die pad 36 serves to support the semiconductor chip 32 fixed thereon during a fabrication process for the semiconductor device.
The leads 33 are each formed of a metal material such as an iron-nickel alloy or copper. The wires 34 are each made of a highly conductive metal material such as gold, silver or copper and have a diameter of about 30 um. Exemplary resins for the resin sealer 35 include thermosetting resins such as epoxy resins.
The semiconductor device is fabricated in the following manner. First, the semiconductor chip 32 is fixed onto the die pad 36 with an adhesive such as of a thermosetting resin, and then the electrodes 31 of the semiconductor chip 32 are respectively connected to the leads 33 through the wires 34. Thereafter, the resulting structure is sealed with the sealing resin in a mold, and the leads 33 extending out of the resin sealer 35 are each formed into an external connection terminal having a predetermined configuration. Thus, the semiconductor device is completed.
In the common semiconductor device shown in FIG. 22, ends of the plural leads on the side of the semiconductor chip 32 are disposed in the vicinity of the semiconductor chip 32 in the same plane to surround the semiconductor chip 32. Portions of the leads 33 extend out of the resin sealer 35 in two or four directions and are equidistantly spaced.
Thus, the common semiconductor device has a clearance for connecting the wires 34 to the leads 33 on the lateral sides of the semiconductor chip 32 and a clearance for forming external connection terminals of the leads 33 outside the resin sealer 35.
Meanwhile, semiconductor devices have recently been developed which have a reduced size substantially equivalent to the size of a semiconductor chip incorporated therein. The downsized semiconductor devices, which are referred to as "CSP (chip size package)", are classified into three major types.
FIG. 23 is a schematic diagram illustrating the construction of a conventional downsized semiconductor device of a first type. The semiconductor device of this type has a construction as disclosed in "EIAJ 2nd Surface Mounting Technology Forum '94 Information".
As shown, the semiconductor device basically includes a semiconductor chip 42 having electrodes 41 formed on a surface thereof on a circuit side, leads 43, wires 44 connecting the electrodes 41 to the leads 43, and a resin sealer 45. The semiconductor chip 42 is fixed to the leads 43 by an insulating tape 46. The leads 43 exposed out of the resin sealer 45 serve as external connection terminals 47.
The semiconductor device of the first type is fabricated in the following manner. First, the semiconductor chip 42 is fixed onto the leads 43 by the insulating tape 46, and then the electrodes 41 of the semiconductor chip 42 are respectively connected to the leads 43 through the wires 44. Thereafter, the resulting structure is sealed with a resin in a mold, and portions of the leads 43 extending out of the resin sealer 46 are trimmed. Thus, the semiconductor device is completed.
One feature of the semiconductor device of the first type is that the leads are used as external connection terminals, like the aforesaid common semiconductor device. In the semiconductor device of the first type, ends of the leads 43 are spaced apart from the surface of the semiconductor chip 42 on the circuit side with intervention of the insulating tape 46. Therefore, when viewed from the top thereof, the semiconductor chip 42 overlaps the leads 43.
With this construction, the electrodes 41 of the semiconductor chip 42 are connected to the leads 43 through the wires 44 within a region just below the semiconductor chip 42. Since a clearance around the periphery of the semiconductor chip can be reduced which is otherwise required for the connection of the leads and the electrodes in the case of the common semiconductor device, the semiconductor device of the first type has a reduced size.
Further, portions of the leads 43 extending out of the resin sealer 45 are trimmed on peripheral surfaces of the resin sealer 45 so that the trimmed sections of the leads 43 serve as the external connection terminals 47. Therefore, the portions of the leads extending out of the resin sealer 45 can be eliminated which otherwise serve as the external connection terminals in the common semiconductor device. Thus, the semiconductor device of the first type has a reduced size substantially equivalent to the size of the semiconductor chip 42.
FIG. 24 is a schematic diagram illustrating the construction of a conventional downsized semiconductor device of a second type. The semiconductor device of this type has a construction as disclosed in Japanese Unexamined Patent Publication No. HEI 5(1993)-82586.
As shown, the semiconductor device of the second type basically includes an interconnection member 52 of a substrate formed with through-holes 51, a semiconductor chip 54 having electrodes 53 formed on a surface thereof on a circuit side, and a resin sealer 55.
The interconnection member 52 has metal interconnection patterns 56 formed on an upper surface thereof. The interconnection patterns 56 are respectively provided with internal connection regions 57 for connecting to the corresponding electrode 53 of the semiconductor chip 54. On a lower surface of the interconnection member 52 are formed external connection regions 58 respectively connected to the corresponding interconnection patterns 56 through the throughholes 51. The external connection regions 58 are respectively provided with external connection terminals 59 for mount implementation. The electrodes 53 of the semiconductor chip 54 are respectively formed with bump electrodes 60 for connecting the electrodes 53 to the internal connection regions 57.
The semiconductor device is constructed such that: the surface of the semiconductor chip 54 on the circuit side is brought in contact with the upper surface of the interconnection member 52; the semiconductor chip 54 is sealed with the resin sealer 55; and the external connection terminals 59 are formed on the lower surface of the interconnection member 52.
The interconnection member 52 comprises an insulating substrate such as of a ceramic plate or a polyimide film. The interconnection patterns 56 of a metal film including the internal connection regions 57 are formed on the upper surface of the interconnection member 52 (i.e., on the side brought in contact with the semiconductor chip 54 for the bonding thereof). The external connection regions 58 are formed on the lower surface of the interconnection member 52 (i.e., on the side opposite to the semiconductor chip 54). The interconnection patterns 56 are electrically connected to the corresponding external connection regions 58 through the through-holes 51.
In the semiconductor device, the layout of the internal connection regions 57 correspond to the layout of the electrodes 53 of the semiconductor chip 54 to be connected thereto. The electrodes 53 of the semiconductor chip 54 are respectively connected to the corresponding internal connection regions 57 via the bump electrodes 60 of tin or the like. The external connection terminals 59 are formed as solder bumps or the like on the external connection regions 58 of the interconnection member 52.
The semiconductor device has electric circuits respectively extending from the electrodes 53 of the semiconductor chip 54 through the internal connection regions 57, the interconnection patterns 56 and the external connection regions 58 to the corresponding external connection terminals 59. The periphery of the semiconductor chip 54 on the interconnection member 52 is sealed with the resin sealer 55 for protecting the electric circuits from an exterior environment.
In accordance with this construction, there is no component disposed on the outer peripheral sides of the semiconductor chip 54, and the lateral size of the semiconductor device is defined by the size of the semiconductor chip plus the thickness of the resin sealer 55. Thus, the size of the semiconductor chip can be reduced.
Further, the provision of the interconnection patterns 56 between the electrodes 53 of the semiconductor chip 54 and the external connection terminals 59 permits free layout design of the external connection terminals 59 for standardization of the layout of the external connection terminals 59. This permits the external connection terminals 59 to be arranged in an area array, which is advantageous for a semiconductor chip having a multiplicity of electrodes.
FIG. 25 is a schematic diagram illustrating the construction of a conventional downsized semiconductor device of a third type. The semiconductor device of this type has a construction as disclosed in Japanese Unexamined Patent Publication No. HEI 6(1994)-504408.
As shown, the semiconductor device of the third type basically includes a semiconductor chip 62 having electrodes 61 formed on a surface thereof on a circuit side, an interconnection member 63 of a substrate, wires 64 connecting the electrodes 61 of the semiconductor chip 62 to the interconnection member 63, and a resin sealer 65.
The interconnection member 63 has metal interconnection patterns 66 formed on a lower surface thereof. The interconnection patterns 66 are respectively provided with internal connection regions 67. The electrodes 61 of the semiconductor chip 62 are respectively connected to the corresponding internal connection regions 67 through the wires 64. On the lower surface of the interconnection member 63 are further formed external connection regions 68, which are connected to external connection terminals 69 for mount implementation formed on the resin sealer 65.
The semiconductor device is constructed such that: the interconnection member 63 is bonded to the semiconductor chip 62 on the circuit side (i.e., on a side thereof provided with the electrodes 61) without covering the electrodes 61; and the electrodes 61 of the semiconductor chip 62 are respectively connected to the internal connection regions 67 of the interconnection member 63 through the wires 64.
The interconnection member 63 comprises an insulating substrate such as of a ceramic plate or a polyimide film. The semiconductor chip 62 is bonded onto the upper surface of the interconnection member 63. On the lower surface of the interconnection member 63 are formed the internal connection regions 67, the interconnection patterns 66 and the external connection regions 68 for connecting to external connection terminals 69. One end of each of the interconnection patterns 66 is connected to the corresponding internal connection region 67, and the other end thereof is connected to the corresponding external connection region 68.
The semiconductor device of the third type is fabricated in the following manner. After the interconnection member 63 is bonded to the semiconductor chip 62, the electrodes 61 of the semiconductor chip 62 are respectively connected to the corresponding internal connection regions 67 of the interconnection member 63 through the wires 64, and then the interconnection member 63 and the wires 64 are sealed with the resin sealer 65. In turn, portions of the resin sealer 65 on the external connection regions 68 are removed to expose the external connection regions 68, and then solder or the like is deposited on the exposed external connection regions 68 to form bumps protruding from the resin sealer 65 for the formation of the external connection terminals 69.
The semiconductor device has electric circuits respectively extending from the electrodes 61 of the semiconductor chip 62 through the wires 64, the internal connection regions 67, the interconnection patterns 66 and the external connection regions 68 to the corresponding external connection terminals 69. The external connection terminals 69 are arranged in an area array.
In accordance with this construction, there is no component disposed on the outer peripheral sides of the semiconductor chip 62 and, therefore, the size of the semiconductor device can be reduced. Further, the provision of the interconnection patterns 66 between the electrodes 61 of the semiconductor chip 62 and the external connection terminals 69 permits free layout design of the external connection terminals 69 for standardization of the layout of the external connection terminals 69. This permits the external connection terminals 69 to be arranged in an area array, which is advantageous for a semiconductor chip having a multiplicity of electrodes. In addition, since the connection between the electrodes 61 of the semiconductor chip 62 and the internal connection terminals 67 is achieved by the wires 64, this construction can be applied to a semiconductor chip having a different electrode layout.
FIGS. 26 and 27 illustrate constructions of semiconductor devices employing projection electrodes as external connection terminals. The semiconductor devices have constructions as disclosed in Japanese Unexamined Patent Publication No. HEI 6(1994)-112354. These constructions are referred to as "BGA (bowl grid array)".
The semiconductor device shown in FIG. 26 includes two layers of interconnection patterns, a semiconductor chip 72 having electrodes 71, an interconnection member 74 of a substrate formed with through-holes 73, wires 75 connecting the electrodes 71 of the semiconductor chip 72 to the interconnection member 73, and a resin sealer 76.
Upper interconnection patterns 77 are formed on an upper surface of the interconnection member 74 (i.e., on a surface of the interconnection member 74 on the side of the semiconductor chip 72). The upper interconnection patterns 77 are respectively provided with internal connection regions 78. Lower interconnection patterns 79 are formed on a lower surface of the interconnection member 74 (i.e., on a surface of the interconnection member 74 opposite to the semiconductor chip 72). The lower interconnection patterns 79 are respectively provided with external connection regions 80 on which external connection terminals 81 for mount implementation are formed.
The upper interconnection patterns 77 are formed on a peripheral surface portion of the interconnection member 74 which is not used for bonding the semiconductor chip 72 to the interconnection member 74.
Each of the wires 75 is connected to a corresponding electrode 71 of the semiconductor chip 72 at one end thereof and to an internal connection region 78 of a corresponding upper interconnection pattern 77 at the other end thereof. The through-holes 73 are formed on an outer peripheral surface portion of the interconnection member 74. The upper interconnection patterns 77 are respectively electrically connected to the corresponding lower interconnection patterns 79 through the through-holes 73.
Since the semiconductor device has the two layers of interconnection patterns 77 and 79, the external interconnection terminals 81 can be disposed in any positions on the lower surface of the interconnection member 74 including an area just below the semiconductor chip 72. Therefore, the external connection terminals 81 are arranged in an area array on the entire lower surface of the interconnection member 74 of the semiconductor device.
Although the BGA semiconductor device has a size comparable to a semiconductor device of the aforesaid common construction having the same number of external connection terminals, the external connection terminals thereof are arranged at increased intervals. This is advantageous because the mounting of the semiconductor device does not require a high positioning accuracy.
In such a BGA semiconductor device, external connection terminals each having a diameter of 0.76 mm are typically arranged at intervals of 1.27 mm to 1.5 mm. Where the BGA semiconductor device has 313 external connection terminals and a semiconductor chip of about 10 mm.times.10 mm, for example, the semiconductor device has a size of about 35 mm.times.35 mm. In this case, the wire length is about 3.5 mm, and the distance between the periphery of the semiconductor chip and the periphery of the semiconductor device is about 12.5 mm.
The semiconductor device shown in FIG. 27 has a single layer of interconnection patterns. Referring to FIG. 27, an explanation will not be given to components denoted by the same reference numerals as in FIG. 26.
In the semiconductor device, the single-layer interconnection patterns 77 are formed on a peripheral surface portion of an interconnection member 74 which is not used for bonding the semiconductor chip 72 to the interconnection member 74. External connection terminals 81 are disposed in an area of the interconnection member 74 just below the interconnection patterns 77.
Although the semiconductor device has substantially the same construction as the semiconductor device of FIG. 26 having the two layers of interconnection patterns, the external connection terminals 81 are not provided in an area of the interconnection member 74 just below the semiconductor chip 72. In the BGA semiconductor devices shown in FIGS. 26 and 27, the external connection terminals 81 are provided in an area outward from the wire connecting points (internal connection regions 78) of the interconnection member 74.
The conventional semiconductor devices described above, however, suffer from the following problems. The conventional downsized semiconductor device of the first type shown in FIG. 23 uses the leads 43 for deriving the circuits to the external connection terminals 47, and the leads 43 are arranged in rows on the peripheral portion of the resin sealer 45. More specifically, the leads 43 are arranged in two parallel rows, or in four rows surrounding the resin sealer 45.
In such a lead layout, the number of the external connection terminals 47 to be provided on the resin sealer 45 is determined by the peripheral length of the resin sealer 45 and the intervals of the leads 43, like the conventional common semiconductor device. Since the external connection terminals 47 are disposed along the periphery of the resin sealer 45, the size of the semiconductor device is increased with the increase in the number of the external connection terminals.
In the conventional downsized semiconductor device of the second type shown in FIG. 24, the electrodes 53 of the semiconductor chip 54 are connected to the internal connection regions 57 formed on the interconnection member 52 through the tin bumps or the like. The positions of the internal connection regions 57 on the interconnection member 52 should exactly coincide with the positions of the electrodes 53 when the semiconductor chip 54 is mounted on the interconnection member 52.
Therefore, where a semiconductor chip having a different electrode layout is to be used, the same interconnection member 52 is useless. Since the interconnection member 52 cannot be used in common with a plurality of kinds of semiconductor chips, the cost of the semiconductor device is increased.
In the conventional downsized semiconductor device of the third type shown in FIG. 25, the interconnection member 63 is bonded onto the surface of the semiconductor chip 62 formed with the electrodes 61, and the electrodes 61 of the semiconductor chip 62 are connected to the internal connection regions 67 of the interconnection member 63 through the wires 64.
Where the interconnection member 63 is thus disposed on the surface of the semiconductor chip 62 formed with the electrodes 61, a clearance is required above the electrodes 61 of the semiconductor chip 62 for the connection by the wires 64. Therefore, the interconnection member 63 cannot be provided just above the electrodes 61. The external connection terminals 69 of the semiconductor device are respectively provided on the external connection regions 68 formed on the surface of the interconnection member 63. This poses a layout limitation such that the external connection terminals 69 cannot be provided just above the electrodes 61 of the semiconductor chip 62. The internal connection regions 67 and the external connection regions 68 are formed in the same plane on the interconnection member 63. This poses a layout limitation such that the external connection terminals 69 cannot be provided above the internal connection regions 67.
In the semiconductor devices shown in FIGS. 26 and 27, the interconnection patterns 77 are provided on the surface of the interconnection member 74 on the side of the semiconductor chip 72. More specifically, the interconnection patterns 77 are provided on the peripheral surface portion of the interconnection member 74 around the semiconductor chip 72. Therefore, the size of the interconnection member 74 is larger than the size of the semiconductor chip 72 by the area formed with the interconnection patterns 77. This results in an increased size of the resin sealer 76, which is much greater than the size of the semiconductor chip 72. Therefore, it is difficult to provide a CSP semiconductor device in which the size of the resin sealer is substantially equivalent to the size of the semiconductor chip 72.